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IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 1 97600 features ? ? wide ? input ? application ? 1.5v D 16v ? ? single ? 3.3v ? or ? single ? 5v ? application ? ? ? output ? voltage ? range: ? 0.6v ? to ? 0.75*vin ? ? 0.5% ? accurate ? reference ? voltage ? ? programmable ? switching ? frequency ? up ? to ? 1.5mhz ? ? programmable ? soft \ start ? ? enable ? input ? with ? voltage ? monitoring ? capability ? ? remote ? sense ? amplifier ? with ? true ? converter ? voltage ? sensing ?? ? thermally ? compensated ? hiccup ? mode ?? over ? current ? protection ? ? over \ voltage ? protection ? ? pre \ bias ? start ? up ? ? body ? braking ? to ? improve ? transient ? ? integrated ? mosfet ? drivers ? and ? bootstrap ? diode ?? ? operating ? temp: ?\ 40 o cIP1837 ? basic ? application ? circuit ?? description ? the ? IP1837 ? ipowir tm ? is ? an ? easy \ to \ use, ? fully ? integrated ?? and ? highly ? efficient ? dc/dc ? regulator. ? the ? onboard ? pwm ? controller ? and ? mosfets ? make ? IP1837 ? a ? space \ efficient ? solution, ? providing ? accurate ? power ? delivery ? for ? low ? output ? voltage ? and ? high ? current ? applications. ? IP1837 ? is ? a ? versatile ? regulator ? which ? offers ? programmability ? of ? switching ? frequency ? and ? current ? limit ? while ? operating ? in ? wide ? input ? and ? output ? voltage ? range. ? the ? switching ? frequency ? is ? programmable ? from ? 250khz ? to ? 1.5mhz ? for ? an ? optimum ? solution. ?? it ? also ? features ? important ? protection ? functions, ? such ? as ?? pre \ bias ? startup, ? hiccup ? current ? limit ? and ? thermal ? shutdown ? to ? give ? required ? system ? level ? security ? in ? the ? event ? of ? fault ? conditions. ? applications ? ? server ? application ? ? netcom ? applications ? ? embedded ? telecom ? systems ? ? distributed ? point ? of ? load ? power ? architectures ? ?? ? 87 88 89 90 91 92 93 94 95 96 97 3.5 7 10.5 14 17.5 21 24.5 28 31.5 35 iout (a) efficiency (%) vo=3.3v vo=1.8v vin=12v vcc=3.3v room temperature 200 lfm airflow includes biasing loss as well as inductor losses and stray pcb losses ?? ? figure ? 2: ? IP1837 ? efficiency ? IP1837 downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 2 97600 pin ? diagram ? ? vin fb pin 17 pin 6 ss pin 5 pin 16 pin 7 vosm comp pin 15 pin 8 vosp voso rt pin 9 en pin 14 pin 10 vcc pgd pin 13 pin 11 ocset pin 12 pin 4 pvcc biasgnd pin 1 sw pgnd pin 2 pin 3 lgnd ? figure ? 3: ? IP1837 ? package ? bottom ? view ? 7.65mm ? x ? 7.65mm ? lga ? ?? ordering ? information ? package ? tape ? and ? reel ? qty ? part ? number ? lga ? (7.65mm ? x ? 7.65mm ? body) ? 2000 ? IP1837trpbf ? ?? ? j-pcb =2.3 0 c/w downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 3 97600 functional ? block ? diagram ? + ? figure ? 4: ? IP1837 ? simplified ? block ? diagram ? ?? ? ? ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 4 97600 typical ? application ? diagram ? ? ? ? figure ? 5: ? IP1837 ? application ? circuit ? diagram ? for ? a ? 12v ? to ? 1.8v, ? 35a ? point ? of ? load ? converter ? ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 5 97600 pin ? descriptions ? pi n # pi n n am e pi n descri pt i on 1 ? vin ? input ? voltage ? for ? power ? stage. ? bypass ? capacitors ? between ? vin ? and ? pgnd ? should ? be ? connected ? very ? close ? to ? this ? pin ? and ? pgnd ? (pin ? 3). ? 2 ? sw ? switch ? node. ? this ? pin ? is ? connected ? to ? the ? output ? inductor. ? 3 ? pgnd ? power ? ground. ? this ? pin ? should ? be ? connected ? to ? the ? systems ? power ? ground ? plane. ? bypass ? capacitors ? between ? vin ? and ? pgnd ? should ? be ? connected ? very ? close ? to ? vin ? pin ? (pin ? 1) ? and ? this ? pin. ? 4 ? pvcc ? output ? of ? internal ? charge ? pump. ? connect ? a ? 4.7uf ? to ? 10uf ? capacitor ? from ? this ? pin ? to ? local ? bias ? pgnd ? (pin ? 12), ? very ? close ? to ? the ? pins. ? external ? 5v ? may ? also ? be ? connected ? to ? this ? pin ? for ? operation ? from ? 5v ? bias. ? 5 ? ss ? soft ? start; ? a ? capacitor ? from ? ss ? and ? lgnd ? sets ? the ? startup ? timing. ? 6 ? lgnd ? signal ? ground ? for ? internal ? reference ? and ? control ? circuitry. ? 7 ? vosm ? remote ? sense ? amplifier ? input. ? connect ? to ? ground ? at ? the ? load. ? 8 ? vosp ? remote ? sense ? amplifier ? input. ? connect ? to ? output ? at ? the ? load. ? 9 ? rt ? use ? an ? external ? resistor ? from ? this ? pin ? to ? gnd ? to ? set ? the ? switching ? frequency, ? very ? close ? to ? the ? pin. ? 10 ? vcc ? input ? bias ? voltage ? for ? internal ? ic. ? this ? also ? powers ? the ? charge ? pump ? circuit ? in ? the ? ic. ? connect ? a ? 10uf ? capacitor ? from ? this ? pin ? to ? local ? bias ? pgnd ? (pin ? 12), ? very ? close ? to ? the ? pins. ? for ? 5v ? bias ? operation, ? this ? pin ? should ? be ? tied ? to ? ground. ? 11 ? ocset ? current ? limit ? setpoint. ? a ? resistor ? may ? be ? connected ? from ? this ? pin ? to ? sw ? pin ? to ? set ? thresholds ? lower ? than ? those ? allowed ? by ? maximum ? current ? rating ? of ? the ? device. ? 12 ? biasgnd ? this ? pin ? serves ? as ? a ? ground ? for ? the ? mosfet ? drivers. ? it ? should ? be ? connected ? to ? the ? negative ? terminal ? of ? the ? bias ? voltage ? at ? the ? vcc ? and/or ? pvcc ? capacitors. ? 13 ? pgd ? power ? good ? status ? pin. ? output ? is ? open ? collector. ? connect ? a ? pull ? up ? resistor ? from ? this ? pin ? to ? vcc. ? 14 ? en ? enable ? pin ? to ? turn ? on ? and ? off ? the ? ic. ? 15 ? voso ? remote ? sense ? amplifier ? output; ? also ? forms ? an ? input ? to ? the ? power ? good ? comparator ? and ? overvoltage ? comparator. ? 16 ? comp ? output ? of ? error ? amplifier. ? an ? external ? resistor ? and ? capacitor ? network ? is ? typically ? connected ? from ? this ? pin ? to ? fb ? to ? provide ? loop ? compensation. ? 17 ? fb ? inverting ? input ? to ? the ? error ? amplifier. ? this ? pin ? is ? connected ? directly ? to ? the ? output ? of ? the ? regulator ? or ? to ? the ? output ? of ? the ? remote ? sense ? amplifier, ? via ? resistor ? divider ? to ? set ? the ? output ? voltage ? and ? provide ? feedback ? to ? the ? error ? amplifier. ? ? ? ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 6 97600 absolute ? maximum ? ratings ? ? vin ? \ 0.3v ? to ? 25v ? vcc ?\ 0.3v ? to ? 3.9v ? pvcc ? \ 0.3v ? to ? 8v ? (note ? 2) ? sw ?\ 0.3v ? to ? 25v ? (dc), ?\ 4v ? to ? 25v ? (ac, ? 100ns) ? boot ? \ 0.3v ? to ? 33v ? input/output ? pins, ? except ? pgd, ? vosp ? and ? voso ?\ 0.3v ? to ? vcc ? + ? 0.3v ? pgd, ? vosp ? and ? voso ? \ 0.3v ? to ? pvcc ? + ? 0.3v ? (note ? 2) ? pgnd ? to ? lgnd, ? biasgnd ? to ? lgnd, ? vosm ? to ? lgnd ?\ 0.3v ? to ? + ? 0.3v ? storage ? temperature ? range ? \ 55c ? to ? 150c ? junction ? temperature ? range ?\ 40c ? to ? 150c ? esd ? classification ? jedec ? class ? 1c ? (1kv) ? moisture ? sensitivity ? level ? jedec ? level ? 3@250c ? ? note ? 1: ? must ? not ? exceed ? 8v. ? note ? 2: ? pvcc ? must ? not ? exceed ? 7.5v ? for ? junction ? temperature ? between ?\ 10c ? and ?\ 40c. ? stresses ? beyond ? those ? listed ? under ? absolute ? maximum ? ratings ? may ? cause ? permanent ? damage ? to ? the ? device. ? these ? are ? stress ? ratings ? only ? and ? functional ? operation ? of ? the ? device ? at ? these ? or ? any ? other ? conditions ? beyond ? those ? indicated ? in ? the ? operational ? sections ? of ? the ? specifications ? are ? not ? implied. ? these ? devices ? are ? esd ? sensitive, ? observe ? handling ? precautions ? to ? prevent ? electrostatic ? discharge ? damage. ? ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 7 97600 electrical ?? specifications ? recommended ? operating ? conditions ? symbol ? definition ? min ? max ? units ? vin ? input ? voltage ? 1.5 ? 16 ? pvcc ? supply ? voltage ? 4.5 ? 7.5 ? vcc ? supply ? voltage ? 3.13 ? 3.46 ? boot ? to ? sw ? supply ? voltage ? 4.5 ? 7.5 ? v o ? output ? voltage ? 0.6 ? 0.75 ? vin ? v ? i o ? output ? current ? 0 ? 35 ? a ? fs ? switching ? frequency ? 225 ? 1650 ? khz ? t j ? junction ? temperature ?\ 40 ? 125 ? c ? ?? electrical ? characteristics ? unless ? otherwise ? specified, ? these ? specification ? apply ? over, ? 1.5v ? < ? vin ? < ? 16v, ? 3.13v ? < ? vcc ? < ? 3.46v. ? 0 o c ? < ? t j ? < ? 125 o c. ?? typical ? values ? are ? specified ? at ? t a ? = ? 25 o c. ? parameter ? symbol ? conditions ? min ? typ ? max ? unit ? power ? loss ? power ? loss ? p loss ? v in ? = ? 12v, ? v cc ? = ? 3.3v, ? v o ? = ? 1.8v, ?? i o ? = ? 35a, ? fs ? = ? 600khz, ? l=0.215uh, ? t a ? = ? 25c ? ?? 7.12 ?? ?? w ? mosfet ? r ds(on) ? top ? switch ? rds(on)_top ?? v boot ? C ? v sw ? = ? 5v, ? i d ? = ? 5a, ? tj ? = ? 25c ?? ? 4.8 ? 6 ?? pvcc ? = ? 5v, ? i d ? = ? 25a, ? tj ? = ? 25c ?? ? 1.45 ? 1.64 ? bottom ? switch ?? ? vcc ? = ? 3.3v, ? i d ? = ? 25a, ? tj ? = ? 25c ?? ? 1.2 ? 1.35 ? m ?? reference ? voltage ? feedback ? voltage ? v fb ?? ? ? ? 0.6 ?? ? v ? 40c ? < ? tj ? < ? 105c ?\ 0.5 ?? ? +0.5 ? accuracy ?? ? \ 40c ? < ? tj ? < ? 125c, ? note ? 3 ?\ 1.5 ?? +1.5 ? % ? supply ? current ? vcc ? supply ? current ? (standby) ? i cc(standby) ? enable ? low, ? no ? switching, ? vcc ? = ? 3.3v ? ?? 400 ? 600 ? ua ? vcc ? supply ? current ? (dyn) ? i cc(dyn) ? enable ? high, ? fs ? = ? 500khz, ? vcc ? = ? 3.3v ? ??? ?? 95 ? ma ? pvcc ? supply ? current ? (standby) ? i pcc(standby) ? enable ? low, ? no ? switching, ? pvcc ? = ? 5v ? ?? 150 ? 200 ? ua ? pvcc ? supply ? current ? (dyn) ? i pcc(dyn) ? enable ? high, ? fs ? = ? 500khz, ? pvcc ? = ? 5v ?? ? ? ? 36 ? ma ? under ? voltage ? lockout ? pvcc ? C ? start ? C ? threshold ? pvcc_uvlo_start ? pvcc ? rising ? trip ? level ? 4.0 ? 4.2 ? 4.4 ? pvcc ? C ? stop ? C ? threshold ? pvcc_uvlo_stop ? pvcc ? falling ? trip ? level ? 3.7 ? 3.9 ? 4.1 ? v ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 8 97600 parameter ? symbol ? conditions ? min ? typ ? max ? unit ? vcc ? C ? start ? C ? threshold ? vcc_uvlo_start ? vcc ? rising ? trip ? level ? 2.6 ? 2.8 ? 3.1 ? vcc ? C ? stop ? C ? threshold ? vcc_uvlo_stop ? vcc ? falling ? trip ? level ? 2 ? 2.2 ? 2.5 ? enable ? C ? start ? C ? threshold ?? enable_uvlo_start ? supply ? ramping ? up ? 1.14 ? 1.2 ? 1.36 ? enable ? C ? stop ? C ? threshold ?? enable_uvlo_stop ? supply ? ramping ? down ? 0.9 ? 1.0 ? 1.06 ? v ? oscillator ? rt ? voltage ?? ? ?? ?? 1 ?? ? v ? ?? 450 ? 500 ? 550 ? frequency ? range ? f s ? ?? 1350 ? 1500 ? 1650 ? khz ?? ramp ? offset ? ramp ? (os) ? note ? 3 ?? 0.4 ?? ? v ? min ? pulse ? width ? dmin ? (ctrl) ? note ? 3 ?? ? 50 ? ns ? fixed ? off ? time ?? note ? 3 ?? 130 ? 200 ? ns ? max ? duty ? cycle ? dmax ?? 75 ?? ? % ? error ? amplifier ? input ? bias ? current ? ifb(e/a) ?? ? \ 1 ?? ? +1 ? a ? input ? bias ? current ? ivp(e/a) ?? ? \ 1 ?? ? +1 ? a ? sink ? current ? isink(e/a) ?? ? 0.6 ? 0.9 ? 1.2 ? ma ? source ? current ? isource(e/a) ?? ? 5 ? 8 ? 12 ? ma ? slew ? rate ? sr ? note ? 3 ? 7 ? 12 ? 20 ? v/s ? gain \ bandwidth ? product ? gbwp ? note ? 3 ? 20 ? 30 ? 40 ? mhz ? dc ? gain ? gain ? note ? 3 ? 100 ? 110 ? 120 ? db ? maximum ? voltage ? vmax(e/a) ?? 1.7 ? 2 ? 2.3 ? v ? minimum ? voltage ? vmin(e/a) ?? ?? 100 ? mv ? remote ? sense ? differential ? amplifier ??? unity ? gain ? bandwidth ? bw_rs ? note ? 3 ? 3 ? 6.4 ? 9 ? mhz ? dc ? gain ? gain_rs ? note ? 3 ?? 110 ?? db ? offset ? voltage ? offset_rs ?? \ 3 ? 0 ? 3 ? mv ? source ? current ? isource_rs ?? 3 ? 9 ? 20 ? ma ? sink ? current ? isink_rs ?? ? 0.4 ? 1 ? 2 ? ma ? slew ? rate ? slew_rs ? note ? 3, ? cload ? = ? 100pf ? 2 ? 4 ? 8 ? v/s ? vosen+ ? input ? impedance ? rin_rs+ ?? ? 70 ?? 120 ? 200 ? kohm ? vosen \? input ? impedance ? rin_rs \? note ? 3 ? 70 ? 120 ? 200 ? kohm ? maximum ? voltage ? vmax_rs ? v(pvcc) ? C ? v(vosp) ? 0.5 ? 1 ? 1.5 ? v ? minimum ? voltage ? min_rs ?? ? 50 ?? mv ? soft ? start ? soft ? start ? charge ? current ? iss_charg ?? ? 14 ? 20 ? 26 ? a ? clamp ? voltage ? vss ? (clamp) ?? ? 3 ? 3.3 ? 3.6 ? a ? offset ? voltage ? vss ? (offset) ?? ? 100 ? 170 ? 250 ? mv ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 9 97600 parameter ? symbol ? conditions ? min ? typ ? max ? unit ? shutdown ? output ? threshold ? sd ?? ? ?? ?? 0.1 ? v ? bootstrap ? diode ? forward ? voltage ?? ? i(boot) ? = ? 30ma, ? note ? 3 ? 360 ? 520 ? 960 ? mv ? switch ? node ? sw ? leakage ? current ? lsw ? sw ? = ? 0v, ? enable ? = ? 0v ?? ? ? 3 ? a ? charge ? pump ? (pvcc) ? output ? voltage ? pvcc ? vcc ? = ? 3.3v, ? fs ? = ? 1500 ? khz, ?? cload ? = ? 2.2uf ? 5.5 ? 6 ? 6.5 ? v ? oscillator ? frequency ? fs_cp ?? ? ? fs ?? ? khz ? body ? braking ? bb ? threshold ? bb_threshold ? fb ? > ? vref, ? sw ? duty ? cycle ?? ? 0 ?? ? % ? power ? good ? power ? good ? lower ? threshold ? vpg ? (lower) ? voso ? rising ? 0.48 ? 0.51 ? 0.54 ? v ? lower ? threshold ? delay ? vpg ? (lower)_dly ? voso ? rising ?? ? 256/fs ?? ? s ? pgood ? voltage ? low ? pg ? (voltage) ?? i pgood ? = ?\ 5ma ?? ? ? ? 0.5 ? v ? leakage ? current ? i leakage ?? ? ? ? 0 ? 1 ? a ? over ? voltage ? protection ? (ovp) ?? ovp ? trip ? threshold ? ovp ? (trip) ? voso ? rising ? 0.67 ? 0.7 ? 0.73 ? v ? ovp ? fault ? prop ? delay ? ovp ? (delay) ? voso ? rising, ? note ? 3 ?? ? ? ? 200 ? ns ? over \ current ? protection ? oc ? trip ? current ? i trip ? oc ? set ? pin ? left ? floating, ?? pvcc ? = ? 6.5v, ? tj ? = ? 85c ? 44 ? 49 ? 54 ? a ? ss ? off ? time ? ss_hiccup ? note ? 3 ? ?? 4096/ fs ? ?? s ? thermal ? shutdown ? thermal ? shutdown ?? ? note ? 3 ?? 145 ?? ? c ? hysteresis ?? ? note ? 3 ?? 20 ?? ? c ? notes ?? 3. ? guaranteed ? by ? design ? but ? not ? tested ? in ? production. ? ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 10 97600 typical ? operating ? characteristics ? ( \ 40c ?\? 125c) ? icc (standby) 200 240 280 320 360 400 440 480 520 560 600 -40 -20 0 20 40 60 80 100 120 temp[ 0 c] [ua] i pvcc (standby) 40 60 80 100 120 140 160 180 200 -40-20 0 20406080100120 temp[ 0 c] [ua] fs 450 460 470 480 490 500 510 520 530 540 550 -40 -20 0 20 40 60 80 100 120 temp[ 0 c] [khz] v fb 0.591 0.593 0.595 0.597 0.599 0.601 0.603 0.605 0.607 0.609 -40-20 0 20406080100120 temp[ 0 c] [v] + 0.5% - 0.5% vpg (lower) 0.48 0.485 0.49 0.495 0.5 0.505 0.51 0.515 0.52 0.525 0.53 0.535 0.54 -40 -20 0 20 40 60 80 100 120 temp[ 0 c] [v] icc (dyn) 59 62 65 68 71 74 77 80 83 86 89 92 95 -40 -20 0 20 40 60 80 100 120 temp[ 0 c] [ma] i pvcc (dyn) 25 26 27 28 29 30 31 32 33 34 35 -40 -20 0 20 40 60 80 100 120 temp[ 0 c] [ma] iss_charg 14 15 16 17 18 19 20 21 22 23 24 25 26 -40 -20 0 20 40 60 80 100 120 temp[ 0 c] [ua] offset_rs -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 -40-20 0 20406080100120 temp[ 0 c] [mv] ovp (trip) 0.67 0.675 0.68 0.685 0.69 0.695 0.7 0.705 0.71 0.715 0.72 0.725 0.73 -40 -20 0 20 40 60 80 100 120 temp[ 0 c] [v] downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 11 97600 typical ? operating ? characteristics ? ( \ 40c ?\? 125c) vpg (lower) 0.48 0.485 0.49 0.495 0.5 0.505 0.51 0.515 0.52 0.525 0.53 0.535 0.54 -40-20 0 20406080100120 temp[ 0 c] [v] vcc_uvlo_start 2.6 2.65 2.7 2.75 2.8 2.85 2.9 2.95 3 3.05 3.1 -40-20 0 20406080100120 temp [ 0 c] [v] pvcc_uvlo_start 4 4.04 4.08 4.12 4.16 4.2 4.24 4.28 4.32 4.36 4.4 -40-20 0 20406080100120 temp [ 0 c] [v] enable_uvlo_start 1.14 1.16 1.18 1.2 1.22 1.24 1.26 1.28 1.3 1.32 1.34 1.36 -40-20 0 20406080100120 temp[ 0 c] [v] il trip 32 34 36 38 40 42 44 46 48 -40 -20 0 20 40 60 80 100 120 temp[ 0 c] [a] vin=12v vo=1.8v fsw=600khz vcc=3.3v r ocset open ovp (trip) 0.67 0.675 0.68 0.685 0.69 0.695 0.7 0.705 0.71 0.715 0.72 0.725 0.73 -40 -20 0 20 40 60 80 100 120 temp[ 0 c] [v] vcc_uvlo_stop 2 2.05 2.1 2.15 2.2 2.25 2.3 2.35 2.4 2.45 2.5 -40-20 0 20406080100120 temp[ 0 c] [v] pvcc_uvlo_stop 3.7 3.74 3.78 3.82 3.86 3.9 3.94 3.98 4.02 4.06 4.1 -40 -20 0 20 40 60 80 100 120 temp [ 0 c] [v] enable_uvlo_stop 0.9 0.916 0.932 0.948 0.964 0.98 0.996 1.012 1.028 1.044 1.06 -40 -20 0 20 40 60 80 100 120 temp[ 0 c] [v] il trip 28 30 32 34 36 38 40 42 44 -40 -20 0 20 40 60 80 100 120 temp[ 0 c] [a] vin=12v vo=1.8v fsw=600khz pvcc=5v r ocset open downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 12 97600 typical ? operating ? characteristics ? ( \ 40c ?\? 125c) ? ? r dson of control fet over temperature at pvcc=5v 3.5 3.9 4.3 4.7 5.1 5.5 5.9 6.3 6.7 7.1 -40 -20 0 20 40 60 80 100 120 temp[ 0 c] r dson (m ? ) ? ? r dson of sync fet over temperature 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 - 4 0- 2 0 0 2 04 06 08 01 0 01 2 0 temp[ 0 c] r dson (m ? ) rdson@pvcc=5v rdson@vcc=3.3v downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 13 97600 thermal ? de \ rating ? curves ? at ? vcc ? = ? 3.3v ? thermal derating-IP1837 vin-12v vout-1.8v/35a freq-600khz 19 21 23 25 27 29 31 33 35 25 30 35 40 45 50 55 60 65 70 75 80 85 t a (c) i out (a) 0 lfm 100lfm 200lfm 300lfm 400lfm thermal derating-IP1837 vin-12v vout-3.3v/35a freq-600khz 17 19 21 23 25 27 29 31 33 35 25 30 35 40 45 50 55 60 65 70 75 80 85 t a (c) i out (a) 0 lfm 100lfm 200lfm 300lfm 400lfm downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 14 97600 theory ? of ? operation ? ?introduction ? the ? IP1837 ? uses ? a ? pwm ? voltage ? mode ? control ? scheme ? with ? external ? compensation ? to ? provide ? good ? noise ? immunity ? and ? maximum ? flexibility ? in ? selecting ? inductor ? values ? and ? capacitor ? types. ?? the ? switching ? frequency ? is ? programmable ? from ? 250khz ?? to ? 1.5mhz ? and ? provides ? the ? capability ? of ? optimizing ? the ? design ? in ? terms ? of ? size ? and ? performance. ?? IP1837 ? provides ? precisely ? regulated ? output ? voltage ? programmed ? from ? 0.6v ? to ? 0.75*vin ? using ? two ? external ? resistors. ? the ? IP1837 ? is ? capable ? of ? operating ? with ? either ?? a ? 3.3v ? vcc ? bias ? voltage ? (3.13v ? to ? 3.46v) ? or ? a ? pvcc ? bias ? voltage ? from ? 4.5v ? to ? 7.5v, ? allowing ? an ? extended ? operating ? input ? voltage ? range ? from ? 1.5v ? to ? 16v. ?? the ? device ? utilizes ? the ? on \ resistance ? of ? the ? low ? side ? mosfet ? as ? the ? current ? sense ? element; ? this ? method ? enhances ? the ? converters ? efficiency ? and ? reduces ? cost ? by ? eliminating ? the ? need ? for ? external ? current ? sense ? resistor. ?? IP1837 ? includes ? two ? low ? r ds(on) ? mosfets ? using ? irs ? hexfet ? technology. ? these ? are ? specifically ? designed ? for ? high ? efficiency ? applications. ??? biasing ? the ? IP1837 ? the ? IP1837 ? offers ? flexibility ? in ? choosing ? the ? bias ? supply ? voltage ? as ? it ? is ? capable ? of ? operating ? with ? a ? 5v ? bias ? voltage ? as ? well ? as ? a ? 3.3v ? bias ? voltage ? (figure ? 1 ? and ? figure ? 32) ? if ? it ? is ? preferred ? to ? use ? a ? 5v ? bias ? voltage, ? this ? should ? be ? applied ? between ? the ? pvcc ? pin ? and ? the ? local ? bias ? pgnd ? (pin ? 12), ? with ? the ? vcc ? pin ? tied ? to ? the ? local ? bias ? pgnd ? also. ? 5.95 6 6.05 6.1 6.15 6.2 6.25 6.3 6.35 6.4 6.45 6.5 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 fsw (khz) pvcc (v) ? figure ? 6: ? pvcc ? v/s ? switching ? frequency ? (fsw) ? with ? vcc=3.3v ? alternatively, ? if ? operation ? from ? 3.3v ? bias ? is ? desired, ? the ? 3.3v ? supply ? should ? be ? applied ? between ? vcc ? and ? the ? local ? bias ? pgnd. ? an ? internal ? charge \ pump ? whose ? output ? is ? tied ? to ? pvcc, ? roughly ? doubles ? this ? vcc ? voltage. ? this ? should ? be ? preferred ? for ? high ? current ? applications ? which ? may ? benefit ? from ? the ? lower ? rds(on) ? on ? account ? of ? the ? higher ? pvcc ? (almost ? 6.3v, ? from ? figure ? 6), ? which ? forms ? the ? supply ? to ? the ? gate ? drivers. ?? under \ voltage ? lockout ? and ? por ? the ? under \ voltage ? lockout ? circuit ? monitors ? the ? input ? supply ? pvcc ? and ? the ? enable ? input. ? it ? ensures ? that ? the ? mosfet ? driver ? outputs ? remain ? in ? the ? off ? state ? whenever ? either ? of ? these ? two ? signals ? drop ? below ? the ? set ? thresholds. ? normal ? operation ? resumes ? once ? pvcc ? and ? enable ? rise ? above ? their ? thresholds. ? the ? por ? (power ? on ? ready) ? signal ? is ? generated ? when ? all ? these ? signals ? reach ? the ? valid ? logic ? level ? (see ? system ? block ? diagram). ? when ? the ? por ? is ? asserted ? the ? soft ? start ? sequence ? starts ? (see ? soft ? start ? section). ? enable ? the ? enable ? feature ? allows ? another ? level ? of ? flexibility ? for ? start ? up. ? the ? enable ? has ? precise ? threshold ? which ? is ? internally ? monitored ? by ? under \ voltage ? lockout ? (uvlo) ? circuit. ? therefore, ? the ? IP1837 ? will ? turn ? on ? only ? when ? the ? voltage ? at ? the ? enable ? pin ? exceeds ? this ? threshold, ? typically, ? 1.2v ? if ? the ? input ? to ? the ? enable ? pin ? is ? derived ? from ? the ? bus ? voltage ? by ? a ? suitably ? programmed ? resistive ? divider, ? it ? can ? be ? ensured ? that ? the ? IP1837 ? does ? not ? turn ? on ? until ? the ? bus ? voltage ? reaches ? the ? desired ? level. ? only ? after ? the ? bus ? voltage ? reaches ? or ? exceeds ? this ? level ? will ? the ? voltage ? at ? enable ? pin ? exceed ? its ? threshold, ? thus ? enabling ? the ? IP1837. ? therefore, ? in ? addition ? to ? being ? a ? logic ? input ? pin ? to ? enable ? the ? IP1837, ? the ? enable ? feature, ? with ? its ? precise ? threshold, ? also ? allows ? the ? user ? to ? implement ? an ? under \ voltage ? lockout ? for ? the ? bus ? voltage ? v in . ? this ? is ? desirable ? particularly ? for ? high ? output ? voltage ? applications, ? where ? we ? might ? want ? the ? IP1837 ? to ? be ? disabled ? at ? least ? until ? v in ? exceeds ? the ? desired ? output ? voltage ? level. ? figure ? 7a ? shows ? the ? startup ? sequence ? with ? the ? enable ? used ? to ? implement ? a ? precise ? under \ voltage ? lockout ? for ? v in . ?? figure ? 7b. ? shows ? the ? recommended ? start \ up ? sequence ? for ? IP1837, ? when ? enable ? is ? used ? as ? a ? logic ? input. downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 15 97600 ? figure ? 7a: ? normal ? start ? up, ? device ? turns ? on ?? when ? the ? bus ? voltage ? reaches ? 10.2v ? bus voltage (12v) pvcc(5v) or vcc(3.3v) enable > 1.2v ss ? figure ? 7b: ? recommended ? startup ? sequence ?? with ? vcc ? or ? pvcc ?? pre \ bias ? startup ? IP1837 ? is ? able ? to ? start ? up ? into ? pre \ charged ? output, ?? which ? prevents ? oscillation ? and ? disturbances ? of ? the ?? output ? voltage. ?? the ? output ? starts ? in ? asynchronous ? fashion ? and ? keeps ? the ? synchronous ? mosfet ? off ? until ? the ? first ? gate ? signal ? for ? control ? mosfet ? is ? generated, ? following ? which, ? the ? synchronous ? mosfet ? starts ? with ? a ? narrow ? duty ? cycle ? of ? 12.5% ? and ? gradually ? increases ? its ? duty ? cycle ? in ? steps ? of ? 12.5%, ? with ? 32 ? cycles ? at ? each ? step ? until ? the ? end ? of ? pre \ bias. ? ?? vo [v] [tim e] pre-bias voltage figure ? 8: ? pre \ bias ? startup ? at ? the ? end ? of ? the ? pre \ bias ? stage, ? the ? synchronous ? mosfet ? is ? switched ? complementary ? to ? the ? control ? mosfet. ?? figure ? 8 ? shows ? a ? typical ? pre \ bias ? condition ? at ? start ? up. ? hdrv 32 end of pb ldriss ldrv 12.5% 25% 87.5% ... ... ... ... ... 32 32 ... ... ... ... ... ... ... ? figure ? 9: ? pre \ bias ? startup ? pulses ?? soft \ start ? the ? IP1837 ? has ? a ? programmable ? soft \ start ? to ? control ? the ? output ? voltage ? rise ? and ? to ? limit ? the ? current ? surge ? at ? the ? start \ up. ? to ? ensure ? correct ? start \ up, ? the ? soft \ start ? sequence ? initiates ? when ? the ? enable ? and ? vcc ? rise ? above ? their ? uvlo ? thresholds ? and ? generate ? the ? power ? on ? ready ? (por) ? signal. ? the ? internal ? current ? source ? (typically ? 20ua) ? charges ? the ? external ? capacitor ? css ? linearly ? from ? 0v ? to ? vcc. ? figure ? 10 ? shows ? the ? waveforms ? during ? the ? soft ? start. ? the ? start ? up ? time ? can ? be ? estimated ? by: ? ? ? (1) * 0.2 - 0.8 ss ss start i c t ? ? during ? the ? soft ? start ? the ? ocp ? is ? enabled ? to ? protect ? the ? device ? for ? any ? short ? circuit ? and ? over ? current ? condition. ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 16 97600 por vss vout 0.2v 0.8v t1 t2 t3 ? figure ? 10: ? theoretical ? operation ? waveforms ? during ? soft \ start ? operating ? frequency ?? the ? switching ? frequency ? can ? be ? programmed ? between ? 250khz ? C ? 1500khz ? by ? connecting ? an ? external ? resistor ? from ? r t ? pin ? to ? gnd. ? table ? 1 ? tabulates ? the ? oscillator ? frequency ? versus ? r t . ? t able ? 1: ? s witching ? f requency ? vs . ? e xternal ? r esistor ? ( r t ) ? fsw ? (khz) ? r t ? (kohm) ? 250 ? 88.7 ? 300 ? 73.2 ? 400 ? 54.9 ? 450 ? 48.7 ? 500 ? 44.2 ? 600 ? 36.5 ? 800 ? 27.4 ? 1000 ? 22.1 ? 1500 ? 14 ? shutdown ? the ? IP1837 ? can ? be ? shutdown ? by ? pulling ? the ? enable ? pin ? below ? its ? 1 ? v ? threshold. ? this ? will ? tri \ state ? both, ? the ? high ? side ? driver ? as ? well ? as ? the ? low ? side ? driver. ?? temperature \ compensated ?? over \ current ? protection ? the ? over ? current ? protection ? is ? performed ? by ? sensing ? current ? through ? the ? r ds(on) ? of ? low ? side ? mosfet. ? this ? method ? enhances ? the ? converters ? efficiency ? and ? reduces ? cost ? by ? eliminating ? a ? current ? sense ? resistor. ? as ? shown ? in ? figure ? 11, ? an ? external ? resistor ? (r ocset ) ? is ? connected ? between ? ocset ? pin ? and ? the ? switch ? node ? (sw) ? which ? sets ? the ? current ? limit ? set ? point. ?? an ? internal ? current ? source ? sources ? current ? ( i ocset ? ) ? out ? of ? the ? ocset ? pin. ? the ? internal ? current ? source ? develops ? a ? voltage ? across ? rocset . ? when ? the ? low ? side ? mosfet ? is ? turned ? on, ? the ? inductor ? current ? flows ? through ? q2 ? and ? results ? in ? a ? voltage ? at ? ocset ? which ? is ? given ? by: ? (2) ) ( ) ( ) l (on ds ocset ocset ocset i r r i v ? ? ? ? an ? over ? current ? is ? detected ? if ? the ? ocset ? pin ? goes ? below ? ground. ? hence, ? at ? the ? current ? limit ? threshold, ? v ocset =0. ? then, ? for ? a ? current ? limit ? setting ? i ltrip , ? r ocset ? is ? calculated ? as ? follows: ? i i r r ocset ltrip on ds ocset (3) * )( ? hiccup control q1 pgnd vin q2 intv cc + - r ocset(int) r ocset(ext) r ocset ocset i ocset sw ? figure ? 11: ? connection ? of ? over \ current ? sensing ? resistor ? it ? should ? be ? noted ? that ? the ? IP1837 ? uses ? a ? temperature ? compensated ? overcurrent ? protection ? scheme, ? i.e., ? i ocset ? varies ? with ? temperature ? with ? the ? same ? temperature ? coeffecient ? as ? r ds(on) , ? so ? that ? i ltrip ? depends ? only ? on ? rocset ? and ? is ? independent ? of ? temperature. ?? the ? value ? of ? rocset ? calculated ? above ? is ? realized ? as ? a ? parallel ? combination ? of ? an ? internal ? 2.7k ? resistor ? and ? an ? external ? resistor ? connected ? between ? the ? rocset ? and ? sw ? pins. ? table ? 2 ? shows ? the ? selection ? of ? the ? external ? rocset ? resistor ? for ? various ? values ? of ? the ? trip ? load ? current ? i otrip ?? at ?? vcc ? = ? 3.3v. ? ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 17 97600 an ? overcurrent ? detection ? trips ? the ? ocp ? comparator, ? latches ? ocp ? signal ? and ? cycles ? the ? soft ? start ? function ? in ? hiccup ? mode. ? the ? hiccup ? is ? performed ? by ? shorting ? the ?? soft \ start ? capacitor ? to ? ground ? and ? counting ? the ? number ? of ? switching ? cycles. ? the ? soft ? start ? pin ? is ? held ? low ? until ? 4096 ? cycles ? have ? been ? completed. ?? following ? this, ? the ? ocp ? signal ? resets ? and ? the ? converter ? recovers. ? after ? every ? soft ? start ? cycle, ? the ? converter ? stays ? in ? this ? mode ? until ? the ? overload ? or ? short ? circuit ? is ? removed. ?? for ? the ? IP1837, ? the ? sync ? fet ? is ? turned ? off ? on ? the ? falling ? edge ? of ? a ? pwmset ? or ? clock ? signal ? that ? has ? a ? duration ? of ? 25% ? of ? the ? switching ? period. ?? for ? operation ? at ? the ? maximum ? duty ? cycle, ? the ? ocp ? circuit ? samples ? current ? for ? 40 ? ns, ? starting ? 40 ? ns ? after ? the ? low ? drive ? signal ? for ? the ? sync ? fet ? > ? 70% ? of ? pvcc. ? t able ? 2: ? o vercurrent ? setting ? vs . ? e xternal ? r ocset ? ? i otrip ? (a) ? external ? rocset ? (kohm) ? 25 ? 4.02 ? 26 ? 4.42 ? 27 ? 4.87 ? 28 ? 5.4 ? 29 ? 6.04 ? 30 ? 6.8 ? 31 ? 7.68 ? 32 ? 8.66 ? 33 ? 10 ? 34 ? 11.5 ? 35 ? 13.7 ? 36 ? 16.2 ? 37 ? 20 ? 38 ? 26.1 ? 39 ? 35.7 ? 40 ? 54.9 ? 41 ? 113 ? 42 ? open ? ?for ? operating ? duty ? cycles ? less ? than ? the ? maximum ? duty ? cycle ? of ? 75%, ? the ? ocp ? circuit ? still ? samples ? current ? for ? typically ? 40ns, ? but ? starts ? sampling ? 40 ? ns ? after ? the ? rising ? edge ? of ? pwmset ? . ?? thus, ? for ? low ? duty ? cycle ? operation, ? the ? inductor ? current ? is ? sensed ? close ? to ? the ? valley. ? this ? allows ? a ? longer ? delay ? after ? the ? falling ? edge ? of ? the ? switch ? node, ? than ? the ? corresponding ? delay ? for ? an ? over \ current ? sensing ? scheme ? which ? samples ? the ? current ? at ? the ? peak ? of ? the ? inductor ? current. ? this ? longer ? delay ? serves ? to ? filter ? out ? any ? noise ? on ? the ? switch ? node ? and ? hence ? on ? the ? ocset ? pin, ? making ? this ? method ? more ? immune ? to ? false ? tripping. ? thermal ? shutdown ?? temperature ? sensing ? is ? provided ? inside ? IP1837. ?? the ? trip ? threshold ? is ? typically ? set ? to ? 145 o c. ? when ? the ?? trip ? threshold ? is ? exceeded, ? thermal ? shutdown ? turns ?? off ? both ? mosfets ? and ? discharges ? the ? soft ? start ? capacitor. ? automatic ? restart ? is ? initiated ? when ? the ? sensed ? temperature ? drops ? within ? the ? operating ? range. ? there ?? is ? a ? 20 o c ? hysteresis ? in ? the ? thermal ? shutdown ? threshold. ? trimmable ? rising ? edge ? deadband ?? the ? IP1837 ? has ? a ? rising ? edge ? deadband ? that ? is ? post \ package ? trimmable. ? it ? is ? typically ? trimmed ? to ? 5ns \ 10ns ? which ? is ? an ? optimal ? range ? to ? minimize ? switching ? transition ? loss ? and ? at ? the ? same ? time, ? prevent ? cross ? conduction. ? remote ? voltage ? sensing ? true ? differential ? remote ? sensing ? in ? the ? feedback ? loop ? is ? critical ? to ? high ? current ? applications ? where ? the ? output ? voltage ? across ? the ? load ? may ? differ ? from ? the ? output ? voltage ? measured ? locally ? across ? an ? output ? capacitor ? at ? the ? output ? inductor, ? and ? to ? applications ? that ? require ? die ? voltage ? sensing. ?? the ? vosp ? and ? vosm ? pins ? of ? the ? IP1837 ? form ? the ? inputs ? to ?? a ? remote ? sense ? differential ? amplifier ? with ? high ? speed, ? low ? input ? offset ? (post \ package ? trimmed ? to ? +/ \ 3mv) ? and ? low ? input ? bias ? current ? which ? ensure ? accurate ? voltage ? sensing ? and ? fast ? transient ? response ? in ? such ? applications. ? it ? should ? be ? noted, ? however, ? that ? the ? output ? voso ? of ? the ? difference ? amplifier ? also ? forms ? the ? input ? toa ? power ? good ? comparator ? and ? overvoltage ? comparator, ? both ? referenced ? to ? an ? upper ? threshold ? of ? 0.7v ? as ? discussed ? in ? the ? next ? section. ? hence, ? in ? applications ? where ? vo ? > ? 0.6v, ? it ? is ? necessary ? to ? use ? a ? resistive ? divider ? network ? after ? vo ? to ? attenuate ? the ? sensed ? output ? voltage ? signal ? between ? the ? remote ? vo ? and ? the ? remote ? ground ? to ? 0.6v, ? which ? is ? then ? applied ? between ? vosp ? and ? vosm. ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 18 97600 in ? applications ? where ? only ? local ? sensing ? is ? required ? for ? feedback, ? the ? remote ? voltage ? sensing ? pins ? of ? the ? IP1837 ? may ? be ? dedicated ? to ? sensing ? the ? output ? for ? power ? good ? indication ? and ? overvoltage ? protection. ?? power ? good ? output ? and ?? over \ voltage ? protection ? the ? ic ? continually ? monitors ? the ? output ? voltage ? via ? output ? of ? the ? remote ? sense ? amplifier ? (voso ? pin). ? the ? voso ? voltage ? forms ? an ? input ? to ? a ? window ? comparator ? whose ? upper ? and ? lower ? thresholds ? are ? 0.7v ? and ? 0.51v ? respectively. ? hence, ? the ? power ? good ? signal ? is ? flagged ? when ? the ? voso ? pin ? voltage ? is ? within ? pgood ? window, ? i.e., ? between ? 0.51v ? and ? 0.69v, ? as ? shown ? in ? figure ? 12a. ? the ? pgood ? pin ? is ? open ? drain ? and ? it ? needs ? to ? be ? externally ? pulled ? high. ? high ? state ? indicates ? that ? output ? is ? in ? regulation. ? figure ? 12a ? also ? shows ? the ? pgood ? timing ? diagram ? with ? a ? 256 ? cycle ? delay ? between ? the ? voso ? voltage ? entering ? within ? the ? thresholds ? defined ? by ? the ? pgood ? window ? and ? pgood ? going ? high ? if ? the ? output ? voltage ? exceeds ? the ? over ? voltage ? threshold ? 0.7v, ? an ? over ? voltage ? trip ? signal ? is ? asserted; ? this ? will ? turn ? off ? the ? high ? side ? driver ? and ? turn ? on ? the ? low ? side ? driver ? until ? the ? voso ? voltage ? drops ? below ? the ? 0.7v ? threshold. ? both ? drivers ? are ? then ? turned ? off ? until ? a ? reset ? is ? performed ? by ? cycling ? vcc ? (or ? pvcc/enable) ? or ? until ? another ? ovp ? event ? occurs ? turning ? on ? the ? low ? side ? driver ? again. ? figure ? 12b ? shows ? the ? response ? in ? over \ voltage ? condition. ? ss 0 0 0 pgd 256/fs voso 0.2v 0.8v 0.51v 0.7v 256/fs ? figure ? 12a: ? IP1837 ? power ? good ? signal ? timing ? diagram ? hdrv 00 0 ldrv voso 0.7v ss 0 0 pgood 0.6v ? figure ? 12b: ? IP1837 ? signal ? timing ? for ? ovp ? body ? braking tm ?? the ? body ? braking ? feature ? of ? the ? IP1837 ? allows ? improved ? transient ? response ? to ? step \ down ? load ? transients. ? a ? severe ? step \ down ? load ? transient ? would ? cause ? an ? overshoot ? in ? the ? output ? voltage ? and ? drive ? the ? comp ? pin ? voltage ? down ? until ? control ? saturation ? occurs ? demanding ? 0% ? duty ? cycle, ? and ? the ? pwm ? input ? to ? the ? control ? fet ? driver ? is ? kept ? off. ? when ? the ? first ? such ? skipped ? pulse ? occurs, ? the ? IP1837 ? enters ? the ? body ? braking ? mode, ? wherein ? the ? sync ? fet ? is ? also ? turned ? off. ? the ? inductor ? current ? then ? decays ? by ? freewheeling ? through ? the ? body ? diode ? of ? the ? sync ? fet. ? thus, ? with ? body ? braking, ? the ? forward ? voltage ? drop ? of ? the ? body ? diode ? provides ? an ? additional ? voltage ? to ? discharge ? the ? inductor ? current ? faster ? to ? the ? light ? load ? value ? as ? shown ? in ? equations ? 4 ? and ? 5 ? below: ? , , (5) braking body without (4) braking body with l v dt di l v v dt di o l d o l ?? ? ?? ? where ? v d = ? forward ? voltage ? drop ? of ? the ? body ? diode ? of ? the ? sync ? fet. ? the ? body ? braking ? mechanism ? is ? kept ? off ? during ? pre \ bias ? operation. ? also, ? in ? the ? event ? of ? an ? extremely ? severe ? load ? step \ down ? transient ? causing ? an ? ovp, ? the ? body ? brake ? is ? overridden ? by ? the ? ovp ? latch, ? which ? turns ? on ? the ? sync ? fet. ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 19 97600 minimum ? on ? time ? considerations ? the ? minimum ? on ? time ? is ? the ? shortest ? amount ? of ? time ? for ? which ? the ? control ? fet ? may ? be ? reliably ? turned ? on, ? and ? this ? depends ? on ? the ? internal ? timing ? delays. ? for ? the ? IP1837, ?? the ? minimum ? on \ time ? is ? specified ? as ? 50 ? ns ? maximum. ?? any ? design ? or ? application ? using ? the ? IP1837 ? must ? require ? a ? pulse ? width ? that ? is ? at ? least ? equal ? to ? this ? minimum ? on \ time ? and ? preferably ? higher ? than ? 100 ? ns. ? this ? is ? necessary ? for ? the ? circuit ? to ? operate ? without ? jitter ? and ? pulse \ skipping, ? which ? can ? cause ? high ? inductor ? current ? ripple ? and ? high ? output ? voltage ? ripple. ? maximum ? duty ? ratio ? considerations ? for ? the ? IP1837, ? the ? upper ? limit ? on ? the ? operating ? duty ? ratio ? is ? set ? by ? the ? duration ? of ? the ? pwmset ? pulse ? or ? by ? the ? 200 ? ns ? fixed ? off \ time, ? whichever ? is ? higher. ? since ? the ? pwmset ? pulse ? has ? a ? 25% ? duty ? cycle, ? this ? limits ? the ? maximum ? duty ? ratio ? at ? which ? the ? IP1837 ? can ? operate, ? to ? 75%. ? at ? switching ? frequencies ? above ? 1.25 ? mhz, ? however, ? the ? maximum ? duty ? ratio ? is ? set ? by ? the ? 200 ? ns ? fixed ? off \ time. ? thus, ? at ? switching ? frequencies ? above ? 1.25 ? mhz, ? higher ? the ? switching ? frequency, ? the ? lower ? is ? the ? maximum ? duty ? ratio ? at ? which ? the ? IP1837 ? can ? operate. ? figure ? 13 ? shows ? a ? plot ? of ? the ? maximum ? duty ? ratio ? v/s ? the ? switching ? frequency, ? with ? 200 ? ns ? off \ time. ? 66% 67% 68% 69% 70% 71% 72% 73% 74% 75% 76% 250 350 450 550 650 750 850 950 1050 1150 1250 1350 1450 1550 1650 switching frequency (khz) max duty cycle (%) ? ? figure ? 13: ? maximum ? duty ? cycle ? v/s ? switching ? frequency. ? trailing ? edge ? pulse ? width ? modulation ? with ? ramp \ slope ? modulation ? the ? IP1837 ? employs ? trailing ? edge ? pulse ? width ? modulation. ? however, ? unlike ? conventional ? trailing ? edge ? modulators, ? which ? compare ? the ? pwm ? ramp ? with ? the ? output ? of ? the ? error ? amplifier ? or ? the ? comp ? voltage, ? in ? the ? modulation ? scheme ? used ? in ? the ? IP1837, ? the ? slope ? of ? the ? pwm ? ramp ?? is ? modulated ? by ? the ? comp ? voltage ? and ? this ? modulated ? ramp ? is ? then ? compared ? to ? a ? fixed ? reference ? voltage. ?? the ? advantage ? of ? this ? scheme ? is ? that ? comparison ? always ? takes ? place ? at ? a ? fixed ? reference ? irrespective ? of ? the ? duty ? cycle ? of ? operation. ? conventional ? modulators ? suffer ? from ? increased ? noise ? susceptibility ? at ? the ? lower ? duty ? cycles, ? since ? the ? comparison ? takes ? place ? at ? the ? comp ? voltage ? level ? which ? is ? close ? to ? the ? bottom ? of ? the ? pwm ? ramp ? for ? low ? duty ? cycle ? operation. ? figure ? 14 ? shows ? theoretical ? waveforms ? for ? the ? pwm ? ramp ? and ? the ? pwm ? output ? in ? response ? to ? a ? changing ? comp ? voltage. ? figure ? 15 ? shows ? the ? variation ? of ? the ? modulator ? gain ? (f m ) ? with ? the ? duty ? cycle ? (d). ? ? ? figure ? 14: ? theoretical ? waveforms ? for ? the ? new ? pwm ? scheme ? modulator gain = -2e-05d 2 + 0.0156d + 0.4168 0 0.2 0.4 0.6 0.8 1 1.2 1.4 5 10152025303540455055 d(%) modulator gain ? ? figure ? 15: ? modulator ? gain ? (f m ) ? v/s ? duty ? ratio ? (d%) ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 20 97600 design ? procedure ?? application ? information ? design ? example ? the ? following ? example ? is ? a ? typical ? application ? for ? IP1837. ? the ? application ? circuit ? is ? shown ? on ? page ? 1. ? v in ? = ? 12v ? (13.2v ? max) ? v o ? = ? 1.8v ? i o ? = ? 35a ? v o ? (transient) ?? 90mv ? for ? io ? = ? 10.5a ? @ ? 2.5a/s ? v o ? (ripple) ?? 13.5mv ? (0.75%) ? f s ? = ? 600khz ? enabling ? the ? IP1837 ? as ? explained ? earlier, ? the ? precise ? threshold ? of ? the ? enable ? lends ? itself ? well ? to ? implementation ? of ? a ? uvlo ? for ? the ?? bus ? voltage. ? IP1837 vin enable r 1 r 2 ? for ? a ? typical ? enable ? threshold ? of ? v en ? = ? 1.2 ? v ? v r r r v en in (6) 1.2 * 2 1 2 (min) ? ? ? ? (7) min 1 2 en ) in( en v v v r r ? ? ? for ? a ? v in ? (min) ? = ? 10.2v, ? r 1 ? = ? 49.9k ? and ? r 2 ? = ? 7.5k ? is ? a ? good ? choice. ? programming ? the ? frequency ? for ? f s ? = ? 600 ? khz, ? select ? r t ? = ? 36.5 ? k , ? using ? table ? 1. ? output ? voltage ? programming ? output ? voltage ? is ? programmed ? by ? the ? reference ? voltage ? and ? external ? voltage ? divider. ? if ? the ? remote ? sense ? feature ? is ? used, ? the ? divider ? is ? connected ? to ? the ? vosp ? and ? vosm ? pins. ? if ? only ? local ? sensing ? is ? used ? for ? feedback, ? with ? the ? remote ? sense ? amplifier ? used ? only ? in ? the ? over \ voltage ? protection, ? circuit, ? the ? resistive ? divider ? should ? be ? connected ? to ? the ?? fb ? pin. ? for ? this ? design, ? with ? high ? output ? current ? requirements, ? we ? choose ? to ? use ? the ? true ? differential ? remote ? sense ? feature. ? the ? fb ? pin ? is ? the ? inverting ? input ? of ? the ? error ? amplifier, ? which ? is ? internally ? referenced ? to ? 0.6v. ? this ? references ? the ? output ? of ? the ? remote ? sense ? amplifier ? to ? 0.6v ? also. ? in ? order ? to ? satisfy ? this ? condition, ? the ? voltage ? between ? the ? vosp ? and ? vosm ? pins ? of ? the ? error ? amplifier ? should ? be ? 0.6v ? when ? the ? output ? is ? at ? its ? desired ? value. ? the ? output ? voltage ? is ? defined ? by ? using ? the ? following ? equation: ? (8) 1 ? ?? ? ? ?? ? ? ? ? bot top ref o r r v v ? when ? an ? external ? resistor ? divider ? is ? connected ? to ? the ? output ? as ? shown ? in ? figure ? 16. ? equation ? (8) ? can ? be ? rewritten ? as: ? (9) ? ?? ? ? ?? ? ? ? ? ref ref o bot top v v v r r ? IP1837 vout vosp r top r bot ? figure ? 16: ? typical ? application ? of ? the ? IP1837 ?? for ? programming ? the ? output ? voltage ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 21 97600 for ? our ? design, ? r bot ? is ? selected ? to ? be ? 604 ? ohm. ?? this ? selection ? is ? based ? on ? a ? trade \ off ? between ? two ? considerations: ?? 1) ? the ? resistive ? divider ? should ? be ? as ? low ? impedance ? as ? possible ? in ? order ? to ? have ? minimal ? impact ? on ? the ? impedance ? seen ? at ? the ? vosp ? and ? vosm ? pins. ? 2) ? the ? resistive ? divider ? should ? have ? high ? enough ? impedance ? so ? as ? to ? minimize ? the ? bleed ? current ? from ? the ? output. ? hence, ? from ? equation ? (9), ? r top ? = ? 1.21k. ? in ? order ? to ? ensure ? that ? the ? vosp ? and ? vosm ? see ? balanced ? impedances, ? it ? is ? advisable ? to ? use ? r comp ? such ? that: ? (10) ? 402 || ? ? bot top comp r r r ? soft \ start ? programming ? the ? soft \ start ? timing ? can ? be ? programmed ? by ? selecting ? the ? soft \ start ? capacitance ? value. ? from ? (1), ? for ? a ? desired ? start \ up ? time ? of ? the ? converter, ? the ? soft ? start ? capacitor ? can ? be ? calculated ? by ? using: ? (11) 0.033 ) ms ( f) ( ? ? start ss t c ? ? where ? t start ? is ? the ? desired ? start \ up ? time ? (ms). ? for ? a ? start \ up ? time ? of ? 3ms, ? the ? soft \ start ? capacitor ? will ? be ? 0.099 f. ? choose ? a ? 0.1 f ? ceramic ? capacitor. ? input ? capacitor ? selection ?? the ? ripple ? current ? generated ? during ? the ? on ? time ? of ? the ? upper ? mosfet ? should ? be ? provided ? by ? the ? input ? capacitor. ? the ? rms ? value ? of ? this ? ripple ? is ? expressed ? by: ? (12) ) 1( d d i i o rms ? ? ? ? ? (13) in o v v d ? ? where: ? d ? is ? the ? duty ? cycle ? i rms ? is ? the ? rms ? value ? of ? the ? input ? capacitor ? current. ?? io ? is ? the ? output ? current. ? for ? i o =35a ? and ? d ? = ? 0.15, ? the ? i rms ?? = ? 12.5a. ? ceramic ? capacitors ? are ? recommended ? due ? to ? their ? peak ? current ? capabilities. ? they ? also ? feature ? low ? esr ? and ? esl ? at ? higher ? frequency ? which ? enables ? better ? efficiency. ? for ? this ? application, ? it ? is ? advisable ? to ? have ? 7x22uf ? 16v ? ceramic ? capacitors ? ecj \ 3yx1c106k ? from ? panasonic. ? in ? addition ? to ? these, ? although ? not ? mandatory, ? a ? 1x330uf, ? 25v ? smd ? capacitor ? eev \ fk1e331p ? may ? also ? be ? used ? as ? a ? bulk ? capacitor ? and ? is ? recommended ? if ? the ? input ? power ? supply ? is ? not ? located ? close ? to ? the ? converter. ? inductor ? selection ?? the ? inductor ? is ? selected ? based ? on ? output ? power, ? operating ? frequency ? and ? efficiency ? requirements. ? a ? low ? inductor ? value ? causes ? large ? ripple ? current, ? resulting ? in ? the ? smaller ? size, ? and ? a ? faster ? response ? to ? a ? load ? transient ? but ? poor ? efficiency ? and ? high ? output ? noise. ? generally, ? the ? selection ? of ? the ? inductor ? value ? can ? be ? reduced ? to ? the ? desired ? maximum ? ripple ? current ? in ? the ? inductor. ? the ? optimum ? point ? is ? usually ? found ? between ? 20% ? and ? 50% ? ripple ? of ? the ? output ? current. ? for ? the ? buck ? converter, ? the ? inductor ? value ? for ? the ? desired ? operating ? ripple ? current ? can ? be ? determined ? using ? the ? following ? relation: ? ?? (14) * 1 ; s in o o in s o in f i v v v v l f d t t i l v v ?? ? ? ? ? ? ? ? ? ? ? ? ? where: ? v in ? = ? maximum ? input ? voltage ? v 0 ? = ? output ? voltage ? i ? = ? inductor ? ripple ? current ? f s ? = ? switching ? frequency ? t ? C ? turn ? on ? time ? d ? C ? duty ? cycle ? ?if ?? i ?? 35%( i o ), ? then ? the ? output ? inductor ? is ? calculated ? to ? be ? 0.21 h. ? select ? l ? = ? 0.215 ? h. ?? the ? pcdc1008 \ r215emo ? from ? cyntec ? provides ? a ? compact ? inductor ? suitable ? for ? this ? application. ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 22 97600 output ? capacitor ? selection ? the ? voltage ? ripple ? and ? transient ? requirements ? determine ? the ? output ? capacitors ? type ? and ? values. ? the ? criteria ? are ? normally ? based ? on ? the ? value ? of ? the ? effective ? series ? resistance ? (esr). ? however ? the ? actual ? capacitance ? value ? and ? the ? equivalent ? series ? inductance ? (esl) ? are ? other ? contributing ? components. ? these ? components ? can ? be ? described ? as: ? (15) * *8 * * )( )( )( )( )( )( s o l co o in eslo l esro co eslo esro o f c i v esl l v v v esr i v v v v v ? ? ? ?? ? ?? ? ? ? ? ?? ? ?? ?? ?? ? ? v 0 = output voltage ripple i l = inductor ripple current ? since ? the ? output ? capacitor ? has ? a ? major ? role ? in ? the ? overall ? performance ? of ? the ? converter ? and ? determines ? the ? result ? of ? transient ? response, ? selection ? of ? the ? capacitor ? is ? critical. ? the ? IP1837 ? can ? perform ? well ? with ? all ? types ? of ? capacitors. ? as ? a ? rule, ? the ? capacitor ? must ? have ? low ? enough ? esr ? to ? meet ? output ? ripple ? and ? load ? transient ? requirements. ? the ? goal ? for ? this ? design ? is ? to ? meet ? the ? voltage ? ripple ? requirement ? in ? the ? smallest ? possible ? capacitor ? size. ? therefore ? it ? is ? advisable ? to ? select ? ceramic ? capacitors ? due ?? to ? their ? low ? esr ? and ? esl ? and ? small ? size. ? fifteen ? of ? the ? panasonic ? ecj \ 2fb0j226ml ? (22uf, ? 6.3v, ? 3mohm) ? capacitors ? is ? a ? good ? choice. ? feedback ? compensation ? the ? IP1837 ? is ? a ? voltage ? mode ? controller. ? the ? control ? loop ? is ? a ? single ? voltage ? feedback ? path ? including ? error ? amplifier ? and ? error ? comparator. ? to ? achieve ? fast ? transient ? response ? and ? accurate ? output ? regulation, ? a ? compensation ? circuit ? is ? necessary. ? the ? goal ? of ? the ? compensation ? network ? is ? to ? provide ? an ? open \ loop ? transfer ? function ? with ? the ? highest ?? 0 ? db ? crossing ? frequency ? and ? adequate ? phase ? margin ? (greater ? than ? 45 o ). ? the ? output ? lc ? filter ? introduces ? a ? double ? pole, ?\ 40db/ ? decade ? gain ? slope ? above ? its ? corner ? resonant ? frequency, ? and ? a ? total ? phase ? lag ? of ? 180 o ? (see ? figure ? 16). ? the ? resonant ? frequency ? of ? the ? lc ? filter ? is ? expressed ? as ? follows: ? (16) 2 1 o o lc c l f ? ? ? ? ? figure ? 17 ? shows ? gain ? and ? phase ? of ? the ? lc ? filter. ? since ? we ? already ? have ? 180 o ? phase ? shift ? from ? the ? output ? filter ? alone, ? the ? system ? runs ? the ? risk ? of ? being ? unstable. ? f lc frequency -40db/decade 0db 0 gain phase -90 -180 f lc frequency 0db ? ? figure ? 17: ? gain ? and ? phase ? of ? lc ? filter ? the ? IP1837 ? uses ? a ? voltage \ type ? error ? amplifier ? with ?? high \ gain ? (110db) ? and ? wide \ bandwidth. ? the ? output ? of ?? the ? amplifier ? is ? available ? for ? dc ? gain ? control ? and ? ac ? phase ? compensation. ? the ? error ? amplifier ? can ? be ? compensated ? either ? in ? type ? ii ?? or ? type ? iii ? compensation. ?? local ? feedback ? with ? type ? ii ? compensation ? is ? shown ? in ? figure ? 18. ?? this ? method ? requires ? that ? the ? output ? capacitor ? should ? have ? enough ? esr ? to ? satisfy ? stability ? requirements. ?? in ? general ? the ? output ? capacitors ? esr ? generates ? a ? zero ? typically ? at ? 5khz ? to ? 50khz ? which ? is ? essential ? for ? an ? acceptable ? phase ? margin. ? the ? esr ? zero ? of ? the ? output ? capacitor ? is ? expressed ? as ? follows: ? (17) 2 1 o esr *esr*c f ? ? ? ? ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 23 97600 v oso v ref r 9 r 8 c pole c 4 r 3 ve f z f pole e/a z f frequency gain(db) h(s) db fb comp z in ? figure ? 18: ? type ? ii ? compensation ? network ?? and ? its ? asymptotic ? gain ? plot ? the ? transfer ? function ? ( v e /v oso ) ? is ? given ? by: ? (18) 1 )( 48 43 c sr c sr z z s h v v in f oso e ? ?? ?? ? ? the ? (s) ? indicates ? that ? the ? transfer ? function ? varies ? as ? a ? function ? of ? frequency. ? this ? configuration ? introduces ? a ? gain ? and ? zero, ? expressed ? by: ? ?? (20) * * 2 1 (19) 4 3 8 3 c r f r r s h z ? ? ? ? first ? select ? the ? desired ? zero \ crossover ? frequency ? ( f o ): ? ?? s esr o f f f * 1/10 ~ 1/5 f and o ? ? ? use ? the ? following ? equation ? to ? calculate ? r 3 : ? (21) * * * * * 2 8 3 lc m in esr o f f v r f f r ? ? ? where: ? v in ? = ? maximum ? input ? voltage ? f o ? = ? crossover ? frequency ? f esr ? = ? zero ? frequency ? of ? the ? output ? capacitor ? f lc ? = ? resonant ? frequency ? of ? the ? output ? filter ? r 8 ? = ? feedback ? resistor ? ? = ??? v ref /v o ? f m =modulator ? gain ?? to ? cancel ? one ? of ? the ? lc ? filter ? poles, ? place ? the ? zero ? before ? the ? lc ? filter ? resonant ? frequency ? pole: ? (22) * 2 1 * 75.0 % 75 o o z lc z c l f f f ? ? ? ? use ? equations ? (20), ? (21) ? and ? (22) ? to ? calculate ? c 4 . ? one ? more ? capacitor ? is ? sometimes ? added ? in ? parallel ? with ? c 4 ? and ? r 3 . ? this ? introduces ? one ? more ? pole ? which ? is ? mainly ? used ? to ? suppress ? the ? switching ? noise. ? the ? additional ? pole ? is ? given ? by: ? (23) * * * 2 1 4 4 3 pole pole p c c c c r f ? ? ? ? the ? pole ? sets ? to ? one ? half ? of ? the ? switching ? frequency ? which ? results ? in ? the ? capacitor ? c pole: ? (24) 1 1 1 3 4 3 s s pole *f *r c *f *r c ? ? ? ? ? ? for ? a ? general ? solution ? for ? unconditional ? stability ? for ? any ? type ? of ? output ? capacitors, ? and ? a ? wide ? range ? of ? esr ? values, ? we ? should ? implement ? local ? feedback ? with ? a ? type ? iii ? compensation ? network. ? the ? typically ? used ? compensation ? network ? for ? voltage \ mode ? controller ? is ? shown ? in ? figure ? 19. ? again, ? the ? transfer ? function ? is ? given ? by: ? in f oso e z z s h v v ?? ? )( ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 24 97600 by ? replacing ? z in ? and ? z f ?? according ? to ? figure ? 19, ? the ? transfer ? function ? can ? be ? expressed ? as: ? ?? ?? (25) .... ) 1( * 1) ( 1) 1( )( 710 3 4 3 4 3 3 4 8 10 8 7 43 c sr c c c c sr c c sr r r sc c sr sh ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ? ? ? ? ? ? ? ? v oso v ref r 9 r 8 r 10 c 7 c 3 c 4 r 3 ve f z 1 f z 2 f p 2 f p 3 e/a z f z in frequency gain(db) h(s) db fb comp ? figure ? 19: ? type ? iii ? compensation ? network ?? and ? its ? asymptotic ? gain ? plot ? the ? compensation ? network ? has ? three ? poles ? and ? two ? zeros ? and ? they ? are ? expressed ? as ? follows: ? (30) * * 2 1 ) (* * 2 1 (29) * * 2 1 (28) * * 2 1 * * 2 1 (27) * * 2 1 (26) 0 8 7 10 8 7 2 4 3 1 3 3 3 4 3 4 3 3 7 10 2 1 r c r r c f c r f c r c c c c r f c r f f z z p p p ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ?? ? ? ? ? ? ? cross ? over ? frequency ? is ? expressed ? as: ? (31) * * 2 1 * * * * * 7 3 o o m in o c l f v c r f ? ? ? ? based ? on ? the ? frequency ? of ? the ? zero ? generated ? by ? the ? output ? capacitor ? and ? its ? esr, ? relative ? to ? crossover ? frequency, ? the ? compensation ? type ? can ? be ? different. ?? the ? table ? below ? shows ? the ? compensation ? types ? for ?? relative ? locations ? of ? the ? crossover ? frequency. ? compensator ? type ? f esr ? v/s ? f 0 ? output ? capacitor ? type ? ii ? f lc ? < ? f esr ? < ? f 0 ? < ? f s /2 ? electrolytic ? tantalum ? type ? iii ? f lc ? < ? f 0 ? < ? f esr ? tantalum ? ceramic ? the ? higher ? the ? crossover ? frequency, ? the ? potentially ? faster ? the ? load ? transient ? response ? will ? be. ? however, ? the ? crossover ? frequency ? should ? be ? low ? enough ? to ? allow ? attenuation ? of ? switching ? noise. ? typically, ? the ? control ? loop ? bandwidth ? or ? crossover ? frequency ? is ? selected ? such ? that: ? ? ? s o f f * 1/10 ~ 1/5 ? ? the ? dc ? gain ? should ? be ? large ? enough ? to ? provide ? high ?? dc \ regulation ? accuracy. ? the ? phase ? margin ? should ? be ? greater ? than ? 45 o ? for ? overall ? stability. ? for ? this ? design ? we ? have: ? v in ? = ? 12v ? v o ? = ? 1.8v ? ? = ? v ref /v o =0.333 ?? modulator ? gain ? = ? f m ? = ? 0.65, ? from ? figure ? 15 ? v ref ? = ? 0.6v ? l o ? = ? 0.215uh ? c o ? = ? 15x22uf, ? esr ? = ? 3mohm ? each ? it ? must ? be ? noted ? here ? that ? the ? value ? of ? the ? capacitance ? used ? in ? the ? compensator ? design ? must ? be ? the ? small ? signal ? value. ? for ? instance, ? the ? small ? signal ? capacitance ? of ? the ? 22uf ? capacitor ? used ? in ? this ? design ? is ? 12uf ? at ? 1.8v ? dc ? bias ? and ? 600khz ? frequency. ? it ? is ? this ? value ? that ? must ? be ? used ? for ? all ? computations ? related ? to ? the ? compensation. ? the ? small ? signal ? value ? may ? be ? obtained ? from ? the ? manufacturers ? datasheets, ? design ? tools ? or ? spice ? models. ? alternatively, ? they ? may ? also ? be ? inferred ? from ? measuring ? the ? power ? stage ? transfer ? function ? of ? the ? converter ? and ? measuring ? the ? double ? pole ? frequency ? f lc ? and ? using ? equation ? (16) ? to ? compute ? the ? small ? signal ? c o . ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 25 97600 these ? result ? in: ? f lc =25.58khz ? f esr =4.4mhz ? f s /2 =300khz ? select ? crossover ? frequency ? f o =110 ? khz ? since ? f lc IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 26 97600 typical ? operating ? waveforms ? vin=12.0v, ? vcc=3.3v, ? vo=1.8v, ? io=0a ?\? 35a, ? room ? temperature, ? no ? airflow ? ? figure ? 20: ? start ? up ? at ? 35a ? load ? ch 1 :v in , ? ch 2 :v o , ? ch 3 :v ss , ? ch 4 :enable ? ? ? figure ? 22 ? : ? start ? up ? with ? 1v ? pre ? bias ? , ? 0a ? load, ? ch 2 :v o , ? ch 3 :v ss ? ? figure ? 24 ? : ? inductor ? node ? at ? 35a ? load ? ch 2 :lx ? ? figure ? 21 error! ? no ? sequence ? specified. : ? start ? up ? at ? 35a ? load ?? ch 1 :v in , ? ch 2 :v o , ? ch 3 :v ss , ? ch 4 :v pgood ? ? figure ? 23: ? output ? voltage ? ripple, ? 35a ? load ? ch 2 : ? v out ? ? ? figure ? 25: ? short ? (hiccup) ? recovery ? ch 2 :v out ? , ? ch 3 :v ss ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 27 97600 typical ? operating ? waveforms ? vin=12.0v, ? vcc=3.3v, ? vo=1.8v, ? io=3.5a ?\? 14a, ? room ? temperature, ? no ? airflow ?? ? ? ? ? ? figure ? 26: ? transient ? response, ? 3.5a ? to ? 14a ? step ? (2.5a/us) ? ch 2 :v out ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 28 97600 typical ? operating ? waveforms ? vin=12.0v, ? vcc=3.3v, ? vo=1.8v, ? io=3.5a ?\? 14a, ? room ? temperature, ? no ? airflow ?? ? ? ? ? figure ? 27: ? transient ? response, ? 24.5a ? to ? 35a ? step ? (2.5a/us) ? ch 2 :v out downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 29 97600 typical ? operating ? waveforms ? vin=12.0v, ? vcc=3.3v, ? vo=1.8v, ? io=0a ?\? 35a, ? room ? temperature ? ? figure ? 28: ? bode ? plot ? at ? 35a ? load ? shows ? a ? bandwidth ? of ? 104.76khz ? and ? phase ? margin ? of ? 60.247 ? degrees ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 30 97600 typical ? operating ? waveforms ? vin=12.0v, ? vcc=3.3v, ? vo=1.8v, ? io=0a ?\? 35a, ? room ? temperature ? 82 83 84 85 86 87 88 89 90 91 92 93 94 95 2 5 8 1 11 41 72 02 32 62 93 23 5 iout (a) efficiency (%) no airflow 200lfm ? figure ? 29: ? efficiency ? versus ? load ? current ? 0 1 2 3 4 5 6 7 8 2 5 8 1 11 41 72 02 32 62 93 23 5 iout (a) power loss (w) no airflow 200 lfm ? figure ? 30: ? power ? loss ? versus ? load ? current downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 31 97600 thermal ? images ? vin=12.0v, ? vcc=3.3v, ? vo=1.8v, ? io=0a \ 35a, ? room ? temperature, ? 200 ? lfm ? ? figure ? 31: ? thermal ? image ? of ? the ? board ? at ? 35a ? load ? test ? point ? 1 ? is ? IP1837 ? test ? point ? 2 ? is ? inductor ? ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 32 97600 other ? application ? circuits ? ? ? figure ? 32: ? application ? with ? external ? pvcc=5v ? ? ? figure ? 33: ? single ? 5v ? application ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 33 97600 ? pvcc fb comp lgnd pgnd sw ocset vo pgd pgood rt vin=3.3v vin vosp vcc ss en vosm voso biasgnd ? figure ? 34: ? single ? 3.3v ? application ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 34 97600 layout ? considerations ? the ? layout ? is ? very ? important ? when ? designing ? high ? frequency ? switching ? converters. ? layout ? will ? affect ? noise ? pickup ? and ? can ? cause ? a ? good ? design ? to ? perform ? with ? less ? than ? expected ? results. ? make ? all ? the ? connections ? for ? the ? power ? components ? in ?? the ? top ? layer ? with ? wide, ? copper ? filled ? areas ? or ? polygons. ?? in ? general, ? it ? is ? desirable ? to ? make ? proper ? use ? of ? power ? planes ? and ? polygons ? for ? power ? distribution ? and ? heat ? dissipation. ? the ? inductor, ? output ? capacitors ? and ? the ? IP1837 ? should ? be ? as ? close ? to ? each ? other ? as ? possible. ? this ? helps ? to ? reduce ? the ? emi ? radiated ? by ? the ? power ? traces ? due ? to ? the ? high ? switching ? currents ? through ? them. ? the ? input ? capacitors ? should ? be ? placed ? as ? close ? as ? possible ? to ? the ? pgnd ? pad. ? the ? connection ? of ? the ? vin ? pad ? to ? the ? vin ? power ? polygon ? should ? be ? low ? impedance, ? using ? several ? vias ? in ? parallel. ? the ? layout ? must ? ensure ? minimum ? length ? ground ? path ? and ? enough ? copper ? for ? input ? and ? output ? capacitors ? with ? a ? direct ? connection. ? the ? IP1837 ? has ? a ? local ? power ? ground ? pad ? called ? bias ? gnd ? (pin ? 12) ? for ? bypassing ? vcc ? or ? pvcc ? supplies. ? the ? analog ? or ? signal ? ground, ? lgnd, ? is ? used ? as ? a ? separate ? control ? circuit ? ground ? to ? which ? all ? signals ? are ? referenced. ? the ? analog ?? ground ? polygon ? should ? be ? connected ? to ? biasgnd ? through ?? a ? single ? point ? connection ? using ? a ? 0 ? ohm ? resistor, ? at ? a ? location ? away ? from ? noise ? sources. ? the ? pgnd ? pad ? (pin ? 3) ? should ? be ? connected ? to ? system ? power ? ground. ? in ? order ? to ? minimize ? coupling ? switching ? noise ? into ? other ? layers, ? the ? area ? of ? the ? switch ? node ? copper ? should ? be ? kept ? small. ? it ? is ? also ? advisable ? to ? keep ? the ? switch ? node ? copper ? localized ? to ? the ? top ? layer. ? the ? critical ? bypass ? components ? such ? as ? capacitors ? for ?? vcc ? should ? be ? close ? to ? their ? respective ? pins. ? it ? is ? important ? to ? place ? the ? feedback ? components ? including ? feedback ? resistors ? and ? compensation ? components ? close ? to ? fb ? and ? comp ? pins. ?? a ? pair ? of ? sense ? traces ? running ? very ? close ? to ? each ? other ? and ? away ? from ? any ? noise ? sources ? should ? be ? used ? to ? implement ? true ? differential ? remote ? sensing ? of ? the ? voltage. ? if ? remote ? sense ? is ? not ? used, ? the ? output ? voltage ? sense ? trace ? used ? for ? feedback ? should ? be ? tapped ? from ? a ? low ? impedance ? point ? such ? as ? directly ? from ? an ? output ? capacitor. ? the ? ipowir ? package ? is ? a ? thermally ? enhanced ? package. ? based ? on ? thermal ? performance ? it ? is ? recommended ? to ?? use ? at ? least ? a ? 6 \ layers ? pcb. ? figures ? 35a \ f ? illustrates ? the ? implementation ? of ? the ? layout ? guidelines ? outlined ? above, ? on ? the ? irdc1837 ? 6 ? layer ? demoboard. ? ? figure ? 35a: ? irdc1837 ? demoboard ? layout ? considerations ? C ? top ? layer enough ? copper ? & ? minimum ? length ? ground ? path ? between ? input ? and ? output all ? bypass ? caps ? (marked ? in ? cyan) ? should ? be ? placed ? as ? close ? as ? possible ? to ? their ? connecting ? pins biasgnd ? single ? point ? connection ? of ? agnd ? and ? biasgnd ? resistors ? rt ? (marked ? in ? brown) ? should ? be ? placed ? as ? close ? as ? possible ? to ? their ? pins compensation ? parts ? (marked ? in ? dark ? blue) ? should ? be ? placed ? as ? close ? as ? possible ? to ? the ? comp ? pin switch ? node ? should ? have ? small ? area ? and ? should ? be ? localized ? to ? top ? layer ?? ? optional ? on ? board ?? load ? transient ? circuit: ? not ? critical ? switch ? node ? should ? have ? small ? area ? and ? should ? be ? localized ? to ? top ? layer ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 35 97600 ? agnd pgnd gnd vin vout sw vin pgnd lgnd vout vin pgnd ? figure ? 35b: ? irdc1837 ? demoboard ? layout ? considerations ? C ? bottom ? layer ? gnd agnd pgnd ? figure ? 35c: ? irdc1837 ? demoboard ? layout ? considerations ? C ? mid ? layer ? 1 ? sw gnd pgnd ? figure ? 35e: ? irdc1837 ? demoboard ? layout ? considerations ? C ? mid ? layer ? 3 ? sw gnd vin vout ? figure ? 35d: ? irdc1837 ? demoboard ? layout ? considerations ? C ? mid ? layer ? 2 ? sw gnd pgnd ? figure ? 35f: ? irdc1837 ? demoboard ? layout ? considerations ? C ? mid ? layer ? 4 ? remote ? sense ? traces, ? tapped ? at ? a ? low ? impedance ? node, ?? such ? as ? across ? a ? capacitor, ? shielded ? by ? pgnd ? layer ? are ? routed ? very ? close ? to ? each ? other ? and ? away ? from ? sw ? node ? ?? all ? bypass ? caps ?? (marked ? in ? cyan) ?? should ? be ? placed ?? as ? close ? as ? possible ? to ?? their ? connecting ? pins ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 36 97600 metal ? and ? component ? placement ? figure ? 36: ? pcb ? metal ? and ? component ? placement ? ? ?? * ? contact ? international ? rectifier ? to ? receive ? an ? electronic ? pcb ? library ? file ? in ? your ? preferred ? format. downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 37 97600 solder ? resist ? ? it ? is ? recommended ? that ? the ? lead ? lands ? are ? non ? solder ? mask ? defined ? (nsmd). ? the ? solder ? resist ? should ? be ? pulled ? away ? from ? the ? metal ? lead ? lands ? by ? a ? minimum ? of ? 0.025mm ? to ? ensure ? nsmd ? pads. ? ? the ? three ? power ? land ? pads ? should ? be ? solder ? mask ? defined ? (smd), ? with ? a ? minimum ? overlap ? of ? the ? solder ? resist ? onto ? the ? copper ? of ? 0.05mm ? to ? accommodate ? solder ? resist ? mis \ alignment. ?? ? ensure ? that ? the ? solder ? resist ? in \ between ? the ? lead ? lands ? and ? the ? pad ? land ? is ?? 0.15mm ? due ? to ? the ? high ? aspect ? ratio ? of ? the ? solder ? resist ? strip ? separating ? the ? lead ? lands ? from ? the ? power ? pad ? lands. ? figure ? 37: ? solder ? resist ? ? * ? contact ? international ? rectifier ? to ? receive ? an ? electronic ? pcb ? library ? file ? in ? your ? preferred ? format. downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 38 97600 stencil ? design ? ? the ? stencil ? apertures ? for ? the ? lead ? lands ? should ? be ? approximately ? 80% ? of ? the ? area ? of ? the ? lead ? pads. ? reducing ? the ? amount ? of ? solder ? deposited ? will ? minimize ? the ? occurrences ? of ? lead ? shorts. ? if ? too ? much ? solder ? is ? deposited ? on ? the ? three ? power ? land ? pads ? the ? part ? will ? float ? and ? the ? lead ? pads ? will ? be ? open. ? ? the ? maximum ? length ? and ? width ? of ? the ? power ? land ? pads ? stencil ? aperture ? should ? be ? equal ? to ? the ? solder ? resist ? opening ? minus ? an ? annular ? 0.2mm ? pull ? back ? to ? decrease ? the ? incidence ? of ? opens ? to ? the ? lead ? lands ? or ? use ? the ? recommended ? stencil ? design ? below. ? ? ? ? figure ? 38: ? stencil ? design ? ?? * ? contact ? international ? rectifier ? to ? receive ? an ? electronic ? pcb ? library ? file ? in ? your ? preferred ? format. ? downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 39 97600 marking ? information ? ?? ? ? ? ? figure ? 39: ? marking ? information ? package ? information ?? ? ? figure ? 40: ? tape ? and ? reel ? information ?? international ? rectifier ? logo ? yyww xxxxxx 1837pbf assembly ? lot ? code part ? number date ? code a1 ? marking cs factory code downloaded from: http:///
IP1837 highly ? integrated ? 35a single \ input ? voltage, ?? synchronous ? buck ? regulator ? march ? 5, ? 2012 ?? | ?? v1.26 ??? 40 97600 ?? 0.12 [.005] c 2. dimensions are shown in millimeters [inches]. 3. controlling dimension: millimeters 1. dimensioning & tolerancing per asme y14.5m-1994. notes: side view c package body. land pad openings. 4 land pad openings. 5 primary datum c (seating plane) is defined by the 6 bilateral tolerance zone is applied to each side of the 5 0.15 [.006] c 2x 6 b a 0.15 [.006] c 2x 6 7. not to scale. 1.66 [.065] 14x 0.508 x 0.508 4 corner id 7.650 [0.301] 7.650 [0.301] bottom view top view 1.35 2.41 3.62 7.32 0.36 1.43 2.49 3.56 4.63 5.69 6.76 0.28 1.21 2.05 3.86 4.71 7.27 ? figure ? 41: ? mechanical ? outline ? drawing ? ?? ? ? ? ? data ? and ? specifications ? subject ? to ? change ? without ? notice ? 3/11. ? this ? product ? will ? be ? designed ? and ? qualified ? for ? the ? consumer ? market. ? qualification ? standards ? can ? be ? found ? on ? irs ? web ? site. ? ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . www.irf.com ? downloaded from: http:///

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